GitHub

Systolic-Processor-Architecture /DPU_array_matrix_multiplication_3

DPU0: DPU_matrix_multiplication port map(A0,B0,CLK,clear,S03,S01,O0); DPU1: DPU_matrix_multiplication port map(A1,S01,CLK,clear,S14,S12,O1); DPU2: DPU_matrix ...
IEEE

MIRAGE: Micro-Ring-Assisted General Engine with Phase-Error Compensation for Scalable Full-Range Matrix-Vector Multiplication

Abstract: Matrix-vector multiplication (MVM) underpins modern AI workloads, yet scaling it on electronic hardware is increasingly constrained by energy, bandwidth, and latency bottlenecks. Photonic ...
IEEE

Energy Efficient Exact and Approximate Systolic Array Architecture for Matrix Multiplication

Abstract: Deep Neural Networks (DNNs) require highly efficient matrix multiplication engines for complex computations. This paper presents a Systolic Array (SA) architecture incorporating novel exact ...
GitHub

Systolic Matrix-Multiply Accelerator

A parameterized systolic-array matrix-multiply accelerator in SystemVerilog. Implements a weight-stationary dataflow across an NxN grid of pipelined multiply-accumulate (MAC) units, with a control FSM ...