Microchip announced production qualification of its PolarFire MPFS250T SoC FPGA supporting the royalty-free RISC-V open standard ISA. Volume production of the MPFS250T, which provides 254,000 logic ...
Microchip Technology Inc. has claimed the industry’s first RISC-V-based System-on-Chip (SoC) FPGA development kit for the PolarFire SoC FPGA. Delivering a standardized, low-cost development platform ...
BERKELEY, Calif. & SANTA CLARA, Calif.--(BUSINESS WIRE)--Today at the RISC-V Summit, the RISC-V Foundation, a non-profit corporation controlled by its members to drive the adoption and implementation ...
A longtime supporter of the RISC-V (pronounced RISC Five) instruction set architecture (ISA), Microsemi provides tools and RISC-V soft cores for its various FPGA lines, including the recently unveiled ...
Microchip Technology has launched what it says is the industry’s first RISC-V based system-on-chip (SoC) field programmable gate array (FPGA) development kit, available for under $500. The rising ...
Microsemi’s 64-bit RISC-V SoC FPGA is based on its PolarFire FPGA. The approach has a number of advantages, including a simplified design that’s easier to secure. The design is immune to Spectre- and ...
Look upon this conference badge and kiss your free time goodbye. The 2019 Hackaday Superconference badge is an ECP5 FPGA running a RISC-V core in a Game Boy form factor complete with cartridge slot ...
March 26, 2024, SANTA CLARA, Calif. & FRAMINGHAM, Mass.– FPGA technology company Achronix Semiconductor Corporation and Bluespec, Inc., a RISC-V tools and silicon IP company, today announced a family ...
Achronix has teamed up with Bluespec to offer a family of Linux-capable RISC-V soft processors for the Speedster7t FPGA family. “Bluespec’s RISC-V processors now integrate into the Achronix 2D network ...
One of the ways people use FPGAs is to have part of the FPGA fabric hold a CPU. That makes sense because CPUs are good at some jobs that are hard to do with an FPGA, and vice versa. Now that the ...
A technical paper titled “Enabling HW-based Task Scheduling in Large Multicore Architectures” was published by researchers at Barcelona Supercomputing Center, University of Campinas, University of Sao ...